The present invention relates to a semiconductor memory system using a DRAM or the like which can realize a high speed access.
A DRAM has been developed in integration to the highest level among MOS semiconductor memories because of the simplicity of a memory cell in a comparative sense and is now used as a main memory of all kinds of computer based apparatuses. On the other hand, there has been progress in improving memory performance being driven by the rapid increase in capabilities of a microprocessor (MPU) in recent years: various kinds of DRAMs each provided with a high speed data cycle function have been proposed and some are already in early stages of mass production. Typical examples are the so-called synchronous DRAM (SDRAM) in which all I/O data are stored or retrieved in synchronism with a system clock and a double-data-rate SDRAM (DDR-SDRAM) which makes it possible to use both edges of a clock pulse as triggers for access though similar to the former in terms of operation, and the like. In addition to the above described DRAMs, a RAMBUS DRAM (RDRAM) (under specifications of Rambus Inc.) in which data transfer is enabled at a high speed with a protocol-based command, and the like have also been developed and a trend in which a conventional asynchronous DRAM is replaced with a synchronous DRAM can be assured to be a necessity in the future.
A characteristic of such a synchronous DRAM is that the maximal bandwidth is operated at a very high speed. As the maximal bandwidth of the latest SDRAM versions, for example, 100 Mbps has been achieved. A DDR-SDRAM and a R-DRAM are estimated to reach 200 Mbps and 800 Mbps respectively in the future, Such a high bandwidth, however, is realized only in burst access along a limited, specific row direction in a memory space. That is, a speed in a so-called random access operation in which a row address is changed can be attained only on almost the same order as a conventional asynchronous DRAM.
A hierarchical structure of a memory has been adopted as a general measure to cope with this situation in a computer system which adopts a DRAM as the main memory. In a concrete manner, the measure is that a cache memory which is constructed from an SDRAM which can realize a high speed access as compared with a DRAM is interposed between a MPU and the DRAM and data of part of the DRAM is cached in the SDRAM. In this case, a memory access from the MPU is performed on the high speed cache memory, and only when an access instruction enters an address space which is not cached in the cache memory, that is, when a cache miss occurs, an access is performed on the DRAM. A great improvement of a computer performance has been realized by adopting this measure even when operating speeds of the MPU and the DRAM are different from each other.
When a cache miss has occurs, however, read-out from the DRAM comes to be required and especially when a different row address in the same block in the DRAM memory space is accessed, there arises the maximal wait time for the MPU. This problem will be described with reference to FIG. 14 below.
FIG. 14 shows an example of a read operation timing for an SDRAM. When a cache miss occurs in the above described computer system which adopts a hierarchical structure of memory and a necessity of access to an SDRAM as a main memory arises, a [precharge command (Precharge)] is issued to perform precharge to an address which is now activated from the system side at time t1. Subsequently, an [activate command (Active)] is issued from the MPU after a predetermined time has elapsed and a bank corresponding to a necessary memory space is activated. A [read command (Read)] is issued after another specific time has elapsed. Data of a specific burst length is read out from the SDRAM in synchronism with a clock pulse at a time t2 when a specific time elapsed after the issuance of the read command. As shown here, the maximal bandwidth when a read operation is successively performed synchronously with a clock pulse is very high, whereas an effective bandwidth for random access in a cache miss is greatly decreased. That is, it is found that a portion of the time period between the time t1 and the t2 when no data is read out, in other words a wait time as viewed from the MPU side, is long.
In a concrete manner, in the case of the specifications of an SDRAM shown in FIG. 14, the maximal bandwidth in a random access cycle is of the order of 36% of that in a burst cycle at most. There will arise a high possibility for this to be a bottle neck in improving computer performance and therefore, the demand for a high performance DRAM has been increasing in which a high access time and a high speed cycle time are realized. Especially, in a multi-MPU system to which a current high-performance server machine is central, high importance is attached to not only high-speed burst transfer but high speed random access. Besides, in a consumer multi-media system in which real time reproduction of a dynamic image is the main object in the future, as well, a DRAM in which a high-speed random access is enabled in a similar way is considered to be a requirement.
With such demands in the backgrounds, an Enhanced SDRAM (ESDRAM) which has been announced from Enhanced Memory Systems Inc., as shown in FIG. 15, a Virtual Channel Memory (VCM) which has been announced from NEC Corp., as shown in FIG. 16, and the like have been proposed.
As described above, a DRAM, in which a high speed data cycle has been realized; represented by an SDRAM, an RDRAM and the like, suffers a long wait time when an access hit miss requires a random access to occur, which is a problem causing a bottle neck in performance improvement of a system.
In the methods of FIGS. 15 and 16 in each of which a large capacity cache memory is provided in order to realize a high speed access time and a high speed cycle time, the overhead for a chip size is high, which in turn causes a problem that realization of the low cost is harder to achieve.
The present invention has been made in light of the above described circumstances and it is accordingly an object of the present invention to provide a semiconductor memory system and an access control method for a semiconductor memory, in which high speed access is made possible without a specific accessory circuit provided while overhead for a chip size is suppressed.
A semiconductor memory system according to the present invention comprises: a semiconductor memory including a memory cell array in which memory cells are located at intersections between a plurality of bit line pairs and a plurality of word lines, the memory cell array of the semiconductor memory being divided into a plurality of cell array blocks, a decoder circuit for selecting a memory cell of the memory cell array, and a sense amplifier circuit for reading out data on a selected memory cell of the memory cell array; an access circuit for successively conducting access on the cell array blocks of the memory cell array of the semiconductor memory; and a control circuit for performing control to change a cycle time according to an access order of the cell array blocks when successive access is conducted on the cell array blocks of the memory cell array of the semiconductor memory.
The control circuit may perform access control in a first operation mode of a first cycle time when successive access within one cell array block of the memory cell array is conducted, and the control circuit may perform access control in a second operation mode of a second cycle time shorter than the first cycle time of the first operation mode when successive access covering the cell array blocks being apart from each other of the memory cell array is conducted.
When the memory cell array of a semiconductor memory adopts a shared sense amplifier system in which cell array blocks adjacent to each other share a series of sense amplifiers, the control circuit may perform access control in a third operation mode of a third cycle time which is a cycle time between the first cycle time of the first operation mode and the second cycle time of the second operation mode when successive access covering cell array blocks adjacent to each other of the memory cell array is conducted.
Furthermore, the present invention has the characteristics listed below when the third operation mode has been set:
(a) The cell array blocks which are adjacent to each other of the memory cell array of the semiconductor memory may share the series of sense amplifiers including bit line equalizer circuits, and when the third operation mode is set, a bit line equalize operation of a cell array block which is accessed in advance and a word line activate operation of a cell array block which is subsequently accessed may be partly in parallel progressed in the semiconductor memory.
(b) The cell array blocks which are adjacent to each other of the memory cell array of the semiconductor memory may share a series of sense amplifiers which include bit line equalizer circuits, and the semiconductor memory may comprise transfer gates interposed between the series of the sense amplifiers and the cell array blocks, and selectively controlled to be conductive, and when the third operation mode is set, a bit line equalize operation of a cell array block which is accessed in advance and a word line activate operation of a cell array block which is subsequently accessed may be partly in parallel progressed by control on conduction of the transfer gates in the semiconductor memory.
(c) In the memory cell array of the semiconductor memory, the cell array blocks which are adjacent to each other of the memory cell array of the semiconductor memory may share a series of sense amplifiers, the semiconductor memory may comprise transfer gates interposed between the series of sense amplifiers and the cell array blocks and selectively controlled to be conductive, and bit line equalizer circuits which are respectively arranged in the series of sense amplifiers and the cell array blocks, and when the third operation mode is set, a bit line equalizer circuit arranged in the series of the sense amplifiers may be activated ahead of a bit line equalizer circuit arranged in each cell array block in the semiconductor memory.
(d) Furthermore, in the case of (c), the transfer gates between the cell array blocks and the series of the sense amplifiers may be controlled to be non-conductive while the bit line equalize operation in the series of the sense amplifiers or the cell array block are conducted.
According to the present invention, in access control of the semiconductor memory, since a speed control that a plurality of operation modes which are different from one another in cycle time according to the access order of the cell array blocks which are successively accessed are set is introduced, high speed access which cannot be obtained in a conventional DRAM or the like can be achieved without provision of a cache section. In a concrete manner, in a DRAM or the like, a memory cell array is divided into a plurality of cell array blocks from the view points of consumed power and a speed. When successive access is conducted within the same cell array block, since a word line activate operation and a bit line precharge operation should be conducted in a time series manner, access control is performed according to the first operation mode with a first cycle time. When successive access covering independent cell array blocks is conducted, since operations of a bit line precharge and a word line activation can independently be conducted in each cell array block, access control is performed according to the second operation mode with the second cycle time shorter than the first cycle time. When such access control is performed, a high speed operation of the whole of a memory system can be realized, since successive access within the same cell array block is low on a probability in the semiconductor memory which is divided.
Further, when a common sense amplifier circuit system is adopted, word line activation and bit line precharge in sub-cell arrays adjacent to each other can be partly overlapped with each other by control of a transfer gate. When successive access covering adjacent cell array blocks is conducted while the overlap operation is used, the access control can be performed according to the third operation mode with the third cycle time being somewhere between the first operation mode and the second operation mode.
With this method, when successive access covering adjacent sub-cell arrays is conducted, the successive access can be realized with a cycle time faster than successive access within a sub-cell array, though slower than successive access covering dispersed sub-cell arrays.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.